1. Field of the Invention
Embodiments of the present invention relate to semiconductor testing.
2. Description of the Related Art
Testing is an important step in the production of semiconductor devices for use. Typically, partially or fully completed semiconductor devices may be tested by bringing terminals disposed on an upper surface of a device to be tested—also referred to as a device under test (or DUT)—into contact with resilient contact elements, for example, as contained in a probe card assembly, as part of a test system. A test system controller may be coupled to the probe card assembly to send and receive test signals to and from the DUTs over a set of test channels. A test system controller with increased test channels can be a significant cost factor for a test system. Test system controllers have evolved to increase the number of channels and hence the number of devices that can be tested in parallel (sometimes referred to as multi-site testing).
One technique to accommodate testing of components on a wafer with a limited number of test channels is to fan out a signal from a test system controller in the probe card assembly to multiple transmission lines. That is, a test signal normally provided to a single DUT can be fanned out to multiple DUTs in the probe card assembly. This technique can enable testing of an increased number of DUTs during a single touchdown for a fixed number of test system channels. This technique can be referred to as test resource extension (TRE).
In some TRE designs, a tester can generate signals that propagate along a transmission line and reach multiple DUTs through multiple stubs (e.g., short transmission lines) that fan out from the transmission line. In some cases, the DUTs are capacitive, which can cause an increase in the rise and fall times of the test signal applied to the DUTs. This increase in rise/fall time can become more significant as the tester drives more DUTs in parallel. Some techniques to address the increase in rise/fall time for TRE designs are to limit the length of the stubs and/or optimize the topology of the DUT distribution. Such techniques, however, give rise to design constraints and are further limited as test signal frequency increases.
Accordingly, there exists a need in the art for a method and apparatus for testing semiconductor devices that attempts to overcome at least some of the aforementioned deficiencies.